Miniaturization in modern day electronics is starting to shift from the chip level to the printed circuit board connecting the different chips. Embedding active components into printed circuit boards or even flexible substrates is a three dimensional solution to this interconnection problem. The benefits of 3D packaging in general and embedding active components in particular are: improved electrical and thermal performance, a higher degree of miniaturization, and more design flexibility. Traditional chip packaging technologies, using pins or solder balls, are in nature two dimensional solutions. Chips and the accompanying passive components are always placed next to each other, requiring space in between for the routing of the signal tracks. This planar approach limits the minimal length of the signal path. A straight-forward solution to this problem is a three dimensional packaging approach. This technology not only minimizes the length of the signal path, but also provides the possibility of placing termination and decoupling passive components close to the active die.
In EP 1230680 B1 a method for integration of a chip within a Printed Circuit Board (PCB), including at least a printed circuit board bottom layer and a further printed circuit layer, has been disclosed. The chip is permanently fixed to the printed circuit board layer and the composite structure is rigid, i.e., not flexible, due to chip and/or PCB thicknesses and properties.
In U.S. Pat. No. 6,794,273, a method of manufacturing a semiconductor device using a wiring substrate is shown, which includes the steps of:
a) forming a peelable resin layer on a silicon substrate, the peelable resin layer having a lower adhesiveness to the silicon substrate and being easily peelable from the silicon substrate;
b) forming the wiring substrate on the peelable resin layer;
c) mounting a plurality of semiconductor chips on the wiring substrate;
d) forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin;
e) individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate;
f) peeling each of the individualized semiconductor devices from the silicon substrate such that the silicon substrate and the peelable resin layer are separated; and
g) exposing terminals provided on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.